There are increasing demands for 40 nm memory devices with a linewidth of 40 nm and less in order to increase the degree of integration. However, it is very difficult to realize a downscaled memory device having a linewidth of 40 nm or less using a typical planar or recessed gate transistor having 8F2 or 6F2 cell architecture, (the capital letter ‘F’ represents a minimum feature size). Therefore, DRAM devices with 4F2 cell architecture are increasingly demanded because this architecture can improve the degree of integration by 1.5 to 2 times higher without scale-down.
In a vertical channel transistor, a surround type gate electrode is formed to surround an active pillar that extends vertically on a semiconductor substrate, and source and drain regions are formed in upper and lower portions of the active pillar over and under the gate electrode, respectively, so that a channel is vertically formed. Therefore, even though an area of a transistor is reduced, a channel length can be secured.
FIG. 1A illustrates a cross-sectional view of a typical semiconductor device with a vertical channel transistor, and FIG. 1B illustrates a plane view of the typical semiconductor device with the vertical channel transistor.
Referring to FIGS. 1A and 1B, a plurality of pillar structures 100 are formed on a substrate 11. Each of the pillar structures 100 includes a body pillar 12, a head pillar 13, a buffer pattern 14, a hard mask pattern 15, and a capping layer 16. The body pillar 12 and the head pillar 13 forms an active pillar.
A gate dielectric 17 and a gate electrode 18 surround an outer wall of the body pillar 12. A buried bit line 19 is formed in the substrate 11. An interlayer dielectric (ILD) layer 20 fills a trench 19A to isolate neighboring bit lines 19 from each other.
A word line 21 is connected to the gate electrode 18, and is formed in a direction crossing the bit line 19. A storage node contact 22 penetrates the hard mask pattern 15 and the buffer pattern 14, and connects to the head pillar 13.
In a typical semiconductor device, the gate electrode 18 is formed of a polysilicon, and the word line 21 is formed of a metal. Furthermore, the word line 21 is formed using a damascene process.
However, according to the typical semiconductor device, the word line 21 does not have a metal-to-metal connection, but has a metal-to-polysilicon connection because the gate electrode 18 is formed of a polysilicon. This leads to an increase in a total sheet resistance of the word line, which affects a driving current flowing through the word line 21.
For example, the word line 21 does not include only metal layers, but has a chain structure where the gate electrode 18 made of polysilicon is disposed between the metal layers. Accordingly, the sheet resistance of the word line is greatly increased due to the polysilicon layer having a high sheet resistance, which makes it difficult to realize a semiconductor device with high-speed performance.